The SAMPULSE20x2 is a demonstration board for the Furaxa SiGe3 30GHz sampler/pulser IC. The SIGe3 IC is a dual channel sampler pulser chip, and the SAMPULSE20x2 demonstration board contains two 2.4mm combined TDR input/output connectors, one to each sampler/pulser channel in the IC. The SiGe3 IC's two sampler outputs are then sent to to two SMA jacks, the first outputting the sample taken on the rising edge of the sampler clock, and the second containing the sample taken on the falling edge of the sampler clock. The sampler clock input, which must be a square wave, may be set to any frequency from 5MHz to 1GHz, causing the board take two pairs of samples (one on each clock edge) at rates from 5 million to 1 billion per second. A pulser clock input, which may be set to any frequency from 5MHz to 2GHz, and MUST be a square wave (preferably differential) with rise time under 100pS, causes the board to produce concurrent pulses on both of the SiGe3's I/O pins, which produce near-concurrent pulses at the two 2.4mm sampler/pulser TDR input/output connectors.
PULSER/SAMPLER CORE
Furaxa has researched, developed, and characterized
a novel monolithic arrayable pulse and sample aperture
generation technology. Recent results include demonstration
of sub-10ps pulse/aperture generation at repetition
rates up to 3 Billion Pulses/Samples Per Second (BPPS)
with jitter that is estimated at sub-10fs. Further,
simulations in a number of InP DHBT processes exhibit
sub-3ps 20BPPS performance. The IP is process-independent,
and has been achieved in CMOS SOI, InP HBT, SiGe and
GaAs so far. Please contact us regarding your specific
foundry and technical requirements:
The company currently
licenses the sampler/pulser technology for use by application
and market, and is interested in discussing how the
technology can enable our partners' applications. A
short list of characterized Pulser/Sampler Cores is
given below.
CMOS SOI Sampler IP Core
The CMOS Sampler core is
particularly useful in cost-sensitive acquisition applications
such as UWB receivers and other low-power, portable
device applications with bandwidth requirements under
10 GHz. Whether communication or test & measurement,
the CMOS Sampler IP core can yield excellent RF performance
at an attractive price.
CMOS SOI Pulser IP Core
The CMOS Pulser IP Core excels in cost-sensitive
synthesis applications such as remote low-power transmitters,
low-cost, handheld T&M applications, and a range
of solutions in which cost, size, and power must all
be minimized while retaining RF performance. The technology
is particularly well-suited for UWB applications,
allowing direct synthesis of UWB waveforms without
the need for mixers or high-precision filters.
InP HBT Sampler IP Core
The InP HBT Pulser IP Core is made for applications
in which sheer acqusition speed and bandwidth is required.
With over 65 GHz of input bandwidth and a repetition
rate exceeding 3 Billion Samples Per Second (BSPS),
the InP sampler core can form the basis of the RF
front-end in advanced optical EOE interafces, precorrection,
and equalization solutions. Emerging commercial and
military applications are targeted with this cutting-edge
technology.
InP HBT Pulser IP Core
The InP HBT Pulser IP Core enables dynamic
burst and continuous synthesis applications with spectral
content beyond 100 GHz. Used in advanced military
applications, (RADAR, EW, and others) and emerging
industrial research and development, this synthesis
capability extends the boundary of electronics into
a region previously unattained in a monolithic solution.
